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L6565
QUASI-RESONANT SMPS CONTROLLER
QUASI-RESONANT (QR) ZERO-VOLTAGESWITCHING (ZVS) TOPOLOGY s LINE FEED FORWARD TO DELIVER CONSTANT POWER vs. MAINS CHANGE s FREQUENCY FOLDBACK FOR OPTIMIUM STANDBY EFFICIENCY s PULSE-BY-PULSE & HICCUP-MODE OCP s ULTRA-LOW START-UP (< 70A) AND QUIESCENT CURRENT (< 3.5mA) s DISABLE FUNCTION (ON/OFF CONTROL) s 1% PRECISION (@ Tj = 25C) INTERNAL REFERENCE VOLTAGE s 400mA TOTEM POLE GATE DRIVER WITH UVLO PULL-DOWN s BLUE ANGEL, ENERGY STAR, ENERGY 2000 COMPLIANT APPLICATIONS s TV/MONITOR SMPS s AC-DC ADAPTERS/CHARGERS s DIGITAL CONSUMER s PRINTERS, FAX MACHINES, PHOTOCOPIERS AND SCANNERS
s
DIP8(Minidip)
SO-8
ORDERING NUMBERS: L6565N L6565D
DESCRIPTION
The L6565 is a current-mode primary controller IC, specifically designed to build offline Quasi-resonant ZVS (Zero Voltage Switching at switch turn-on) flyback converters. Quasi-resonant operation is achieved by means of a transformer demagnetization sensing input that triggers MOSFET's turn-on.
BLOCK DIAGRAM
COMP 2 1 INV + 2.5V VOLTAGE REGULATOR + 2V + 5pF LINE VOLTAGE FEEDFORWARD 40K 4 CS VFF 3
8 VCC 20V R1 + S INTERNAL SUPPLY
Hiccup-mode OCP R Q
VCC
7 GD DRIVER
R2
VREF2
-
ZERO CURRENT DETECTOR 2.1 V 1.6 V + BLANKING STARTER
Hiccup-mode OCP
DISABLE 6
5 ZCD
GND
December 2001
1/17
L6565
DESCRIPTION (continued)
Converter's power capability variations with the mains voltage are compensated by line voltage feedforward. At light load the device features a special function that automatically lowers the operating frequency still maintaining the operation as close to ZVS as possible. In addition to very low start-up and quiescent currents, this feature helps keep low the consumption from the mains at light load and be Blue Angel and Energy Star compliant. The IC includes also a disable function, an on-chip filter on current sense, an error amplifier with a precise reference voltage for primary regulation and an effective two-level overcurrent protection.
PIN CONNECTION (Top view, Minidip and SO8)
INV COMP VFF CS
1 2 3 4
8 7 6 5
Vcc GD GND ZCD
PIN DESCRIPTION
N 1 Name INV Function Inverting input of the error amplifier. The information on the output voltage is fed into the pin through either a resistor divider (primary regulation) or an optocoupler (secondary feedback). This pin can be grounded in some secondary feedback schemes (see pin 2). Output of the error amplifier. Typically, a compensation network is placed between this pin and the INV pin to achieve stability and good dynamic performance of the voltage control loop. With secondary feedback, the pin can be also driven directly by an optocoupler to control PWM by modulating the current sunk from the pin (with the INV pin grounded). Line voltage feedforward. The information on the converter's input voltage is fed into the pin through a resistor divider and is used to change the setpoint of the pulse-by-pulse current limitation (the higher the voltage, the lower the setpoint). If this function is not desired the pin will be grounded and the current limitation setpoint will be maximum. Input to the PWM comparator. The primary current is sensed through a resistor, the resulting voltage is applied to this pin and compared with an internal reference to determine MOSFET's turn-off. The internal reference is clamped at a value, which defines the pulse-by-pulse current limitation setpoint, depending on the voltage at pin VFF. If the signal at the pin CS exceeds 2 V, the gate driver will be disabled (Hiccup-mode OCP). Transformer's demagnetization sensing input for Quasi-Resonant operation. Alternately, synchronization input for an external signal. A negative-going edge triggers MOSFET's turn-on. The trigger circuit is blanked for a minimum of 3.5 s after MOSFET turn-off, for safe operation under short circuit conditions and frequency foldback. If the pin is grounded the IC will be disabled. Ground. Current return for both the signal part of the IC and the gate driver. Gate driver output. The totem pole output stage is able to drive power MOSFET's and IGBT's with a peak current of 400 mA (source and sink). Supply Voltage of both the signal part of the IC and the gate driver. An electrolytic capacitor is connected between this pin and ground. A resistor connected from this pin to the converter's input bulk capacitor will be typically used to start up the device.
2
COMP
3
VFF
4
CS
5
ZCD
6 7 8
GND GD Vcc
2/17
L6565
THERMAL DATA
Symbol Rth j-amb Parameter Max. Thermal Resistance, Junction-to-ambient SO8 150 Minidip 100 Unit C/W
ABSOLUTE MAXIMUM RATINGS
Symbol IVcc IGD INV, COMP, VFF, CS IZCD Ptot Tj Tstg Pin 8 7 ICC + IZ Output Totem Pole Peak Current (2 s) Parameter Value 30 700 -0.3 to 7 50 (source) -10 (sink) (Minidip ) (SO8) 1 0.65 -40 to 150 -55 to 150 Unit mA mA V mA W C C
1, 2, 3 4 Analog Inputs & Outputs 5 Zero Current Detector Power Dissipation @Tamb = 50C Junction Temperature Operating range Storage Temperature
ELECTRICAL CHARACTERISTCS (Tj = -25 to 125C, VCC = 12V, Co = 1nF; unless otherwise specified)
Symbol SUPPLY VOLTAGE Vcc VCCOn VCCOff Hys VZ Operating range Turn-on threshold Turn-off threshold Hysteresis Zener Voltage Icc = 25 mA After turn-on 10.3 12.5 8.7 3.65 18 13.5 9.5 4 20 18 14.5 10.3 4.3 22 V V V V Parameter Test Condition Min. Typ. Max. Unit
SUPPLY CURRENT Istart-up Iq ICC Iq Iq Start-up Current Quiescent Current Operating Supply Current Quiescent Current Quiescent Current Before turn-on, VCC = 12V After turn-on @ 70 kHz During Hiccup-mode OCP V ZCD < VDIS, VCC>VCCOff 1.6 1.4 45 2.3 3.5 70 3.5 5 3.5 2.1 A mA mA mA mA
LINE FEEDFORWARD IVFF VVFF Input Bias Current Operating Range V VFF = 0 to 3 V 0 to 3 -1 A V
3/17
L6565
ELECTRICAL CHARACTERISTCS (continued) (Tj = -25 to 125C, VCC = 12V, Co = 1nF; unless otherwise specified)
Symbol K Gain Parameter Test Condition V VFF = 1.5V, VCOMP = 4V Min. Typ. 0.14 Max. Unit
ERROR AMPLIFI ER VINV Voltage Feedback Input Threshold Tamb = 25C 12V < VCC < 18V Line Regulation IINV GV GB ICOMP Input Bias Current Voltage Gain Gain-Bandwidth Product Source Current Sink Current VCOMP Upper Clamp Voltage Lower Clamp Voltage CURRENT SENSE COMPARATOR ICS td(H-L) VCSx Input Bias Current Delay to Output Current Sense Reference Clamp
VCOMP = Upper clamp, VVFF = 0V VCOMP = Upper clamp, VVFF = 1.5V
2.465 2.44
2.5
2.535 2.56
V
Vcc = 12 to 18V
2 -0.1
5 -1
mV A dB MHz
Open loop
60
80 1
V COMP = 4V, V INV = 2.4 V V COMP = 4V, V INV = 2.6 V ISOURCE = 0.5 mA ISINK = 0.5 mA
-2 2.5
-3.5 4.5 5.8 2.25
-5
mA mA V V
V CS = 0
-0.05 200 1.32 0.66 0 1.85 2.0
-1 450
A ns V
VCOMP = Upper clamp, VVFF = 3V
VCSdis
Hiccup-mode OCP level
2.2
V
ZERO CURRENT DETECTOR/ SYNCHRONIZATION VZCDH VZCDL VZCDA VZCDT IZCDb IZCDsrc IZCDsnk VDIS Upper Clamp Voltage Lower Clamp Voltage Arming Voltage (positive-going edge) Triggering Voltage (negative-going edge) Input Bias Current Source Current Capability Sink Current Capability Disable Threshold V ZCD = 1 to 4.5 V -3 3 150 200 IZCD = 3mA IZCD = - 3mA
(1)
4.7 0.3
5.2 0.65 2.1 1.6 2
6.1 1
V V V V A
-10 10 250
mA mA mV
4/17
L6565
ELECTRICAL CHARACTERISTCS (continued) (Tj = -25 to 125C, VCC = 12V, Co = 1nF; unless otherwise specified)
Symbol IZCDr TBLANK Parameter Restart Current After Disable Blanking time after pin 7 high-tolow transition Test Condition V ZCD < VDIS, Vcc > Vccoff V COMP 3.2 V V COMP = 2.5 V START TIMER tSTART Start Timer period 250 400 550 s Min. -70 Typ. -150 3.5 18 Max. -230 Unit A s
GATE DRIVER VOL Dropout Voltage IGDsource = 200mA IGDsource = 20mA VOH IGDsink = 200mA IGDsink = 20mA tf tr IGDoff Current Fall Time Current Rise Time IGD sink current Vcc = 4 V, VGD = 1 V 5 40 40 10 1.2 0.7 2 1 2 0.3 100 100 ns ns mA V V
(1) Parameters guaranteed by design, not tested in production.
Figure 1. Supply current vs. Supply voltage
ICC (mA) 10 5 1 0.5 0.1 0.05 0.01 0.005 0 0 5 10 15 20 VCC(V) CL = 1nF f = 70KHz TA = 25C
Figure 2. Start-up & UVLO vs. Temperature
14 VCC-ON (V) 13
12
11
10 VCC-OFF (V) 9 -25
0
25
50
75
100
125
T (C)
5/17
L6565
Figure 3. Feedback reference vs. Temperature
VREF (V)
D94IN048A
Figure 6. ZCD blanking time vs. COMP voltage
TBLANK [s]
20
Tj = 25 C
15
2.50
10
2.48
5
0 2
2.46 -50 0 50 100 T (C)
3
4
5
6
VCOMP [V]
Figure 4. Line feedforward characteristics
Vcsx [V]
1.5
Upper clamp
Figure 7. Gate-drive output saturation
Vpin7 [V]
2.5 2 1.5
Tj = 25 C Vcc = 14.5 V SINK
5.0 V
1
4.5 V
4.0 V
1
0.5
3.5 V
0.5
3.0 V
0
VCOMP = 2.5V
0
1 1.5 2 2.5 3 3.5
0
0.5
0
100
200
300
400
500
VVFF [V]
IGD [mA]
Figure 5. Pin 2 (COMP) V-I characteristics
VCOMP [V]
6 5 4
Tj = 25 C Vpin1 = 0
Figure 8. Gate-drive output saturation
Vpin7 [V]
Vcc - 0.5 0 Vcc --0.5 0.5
Tj = 25 C Vcc = 14.5 V SOURCE
-1 Vcc - 1.0 3 2 1 0 0 1 2 3 4
Regulation range
Vcc --1.5 1.5
-2 Vcc - 2.0
Vcc --2.5 0.5
0
100
200
300
400
500
ICOMP [mA]
IGD [mA]
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L6565
APPLICATION INFORMATION
Quasi-resonant operation in offline flyback converters lies in synchronizing MOSFET's turn-on to the transformer's demagnetization. Detecting the resulting negative-going edge of the voltage across any winding of the transformer can do this. The L6565 is provided with a dedicated pin that allows doing the job with a very simple interface, just one resistor. Variable frequency operation - as a result of different operating conditions in terms of input voltage and output current - is inherent in such functionality. The system always works close to the boundary between DCM (Discontinuous Conduction Mode) and CCM (Continuous Conduction Mode) operation of the transformer. The operation is then identical to that of the so-called self-oscillating or Ringing Choke Converter (RCC).
Detailed Device Description
Internal Supply Block (see fig. 9)
A linear voltage regulator supplied by Vcc (pin 8) generates an internal 7V rail used for supplying the entire IC, except for the gate driver that is supplied directly from Vcc. In addition, a bandgap circuit generates a precise internal reference (2.5V1% @ 25C) used by the control loop to ensure a good regulation with primary feedback technique. In figure 9 it is also shown the undervoltage lockout (UVLO) comparator with hysteresis used to enable the chip as long as the Vcc voltage is high enough to ensure a reliable operation.
Figure 9. L6565 internal supply block
+Vin
Vcc 8
+ LIN. REG. REF. UVLO
2.5V 7V bus
7/17
L6565
Zero Current Detection and Triggering Block (see fig. 10):
The Zero Current Detection (ZCD) block switches on the external MOSFET if a negative-going edge falling below 1.6 V is applied to the input (pin 5, ZCD). However, to ensure high noise immunity, the triggering block must be armed first: prior to falling below 1.6V, the voltage on pin 5 must experience a positive-going edge exceeding 2.1 V. This feature is typically used to detect transformer demagnetization for QR operation, where the signal for the ZCD input is obtained from the transformer's auxiliary winding used also to supply the IC. Alternatively, this can be used to synchronize MOSFET's turn-on to the negative-going edge of an external clock signal, in case the device is not required to work in QR mode but as a standard PWM controller in a synchronized system (e.g. monitor SMPS). The triggering block is blanked for a certain time after the MOSFET has been turned off. This has two goals: first, to prevent any negative-going edge that follows leakage inductance demagnetization from triggering the ZCD circuit erroneously; second, to realize the Frequency Foldback function (see the relevant description).
Figure 10. Zero Current Detection and Triggering Block; Disable and Frequency Foldback Blocks
COMP INV
L6565
+Vin ZCD 5 5.2V BLANKING TIME
E/A
+ 2.5V to line FFWD
PWM
200A
+ Q 0.15V 1.6V 2.1V
+ -
R Q S
DRIVER
7
GD
STARTER DISABLE
A circuit is needed that turns on the external MOSFET at start-up since no signal is coming from the ZCD pin. This is realized with an internal starter, which forces the driver to deliver a pulse to the gate of the MOSFET. To minimize the external interface with the synchronization source (either the auxiliary winding or an external clock), the voltage at the pin is both top and bottom limited by a double clamp, as illustrated in the internal diagram of the ZCD block of figure 10. The upper clamp is typically located at 5.2 V, while the lower clamp is at one VBE above ground. The interface will then be made by just one resistor that has to limit the current sourced by and sunk from the pin within the rated capability of the internal clamps.
Disable Block (see fig. 10):
The ZCD pin is used also to activate the Disable Block. If the voltage on the pin is taken below 150 mV the device will be shut down. To do so, it is necessary to override the source capability (10 mA max.) of the internal lower clamp. While in disable, the current consumption of the IC will be reduced. To re-enable device operation, the pull-down on the pin must be released.
Frequency Foldback Block (see fig. 10):
To prevent the switching frequency from reaching too high values, which is a typical drawback of QR operation,
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L6565
the L6565 puts a limit on the minimum OFF-time of the switch. This is done by blanking the triggering block of the ZCD circuit as mentioned before. The duration of the blanking time (3.5s min.) is a function of the error amplifier output VCOMP, as shown in the diagram of figure 6. If the load current and the input voltage are such that the switch OFF-time falls below the minimum blanking time of 3.5s, the system will enter the "Frequency Foldback" mode, a sort of "ringing cycle skipping" illustrated schematically in figure 11.
Figure 11. Frequency foldback: ringing cycle skipping as the load is progressively reduced
VDS VDS VDS
t TFW TBLANKmin TV TBLANK
t
t
TBLANK
Pin = Pin'
(limit condition)
Pin = Pin'' < Pin'
Pin = Pin''' < Pin''
In this mode, uneven switching cycles may be observed under some line/load conditions, due to the fact that the OFF-time of the MOSFET is allowed to change with discrete steps (2*Tv), while the OFF-time needed for cycle-by-cycle energy balance may fall in between. Thus one or more longer switching cycles will be compensated by one or more shorter ones and vice versa. However, this mechanism is absolutely normal and there is no appreciable effect on the performance of the converter or on its output voltage.
Figure 12. Frequency Foldback: qualitative frequency dependence on power throughput
fsw
Voltage Feedforward block (see fig. 14b):
The power that QR flyback converters with a fixed overcurrent setpoint (like fixed-frequency systems) are able to deliver changes with the input voltage considerably. With wide-range mains, at maximum line it can be more than twice the value at minimum line, as shown by the upper curve in the diagram of figure 13. The L6565 has the Line Feedforward function available to solve this issue.
without frequency foldback Vin fixed
BURST MODE
with frequency foldback
Figure 13. Typical power capability change vs. input voltage in ZVS QR flyback converters
2.5
Pin
2
system not compensated
Further load reductions involve lower values for VCOMP, which increases the blanking time. Therefore, more and more ringing cycles will be skipped. When the load is low enough, so many ringing cycles need to be skipped that their amplitude becomes very small and they can no longer trigger the ZCD circuit. In that case the internal starter of the IC will be activated, resulting in burst-mode operation: a series of few switching cycles spaced out by long periods where the MOSFET is in OFF state.
Pinlim @ Vin Pinlim @ Vinmin
1.5
1 system optimally compensated 0.5 1 1.5 2 2.5 3 3.5 4
Vin Vinmin
9/17
L6565
It acts on the clamp level of the control voltage Vcsx, that is on the overcurrent setpoint, so that it is a function of the converter's input voltage sensed through a dedicated pin (#3, VFF): the higher the input voltage, the lower the setpoint. This is illustrated in the diagram of figure 14a that shows the relationship between the voltage at the pin VFF and Vcsx (with the error amplifier saturated high in the attempt of keeping output voltage regulation). The schematic in figure 14b shows also how the function is included in the control loop. With a proper selection of the external divider R1-R2 it is possible to achieve the optimum compensation described by the lower curve in the diagram of figure 13. In applications where this function is not wanted, e.g. because of a narrow input voltage range, the VFF pin can be simply grounded, thus saving the resistor divider. The overcurrent setpoint will be then fixed at the maximum value of about 1.3 V. Line Feedforward is also beneficial to other characteristics of quasi-resonant converters: it improves their input ripple rejection ability and limits the variation of the power stage's small-signal gain versus the line voltage.
Figure 14. a) Overcurrent setpoint vs. VFF voltage; b) Line Feedforward function block
Vcsx [V]
1.5
VCOMP = Upper clamp
1
a)
0.5
0 0 0.5 1 1.5 2 2.5 3 3.5
VVFF [V]
+Vin
R1
R2
Rs
COMP 2 INV 1 E/A + 3
VFF
CS 4
VOLTAGE FEED FORWARD
Hiccup
2.5V
2V
b)
10/17
+ PWM R Q S +
DRIVER
7
-
GD
DISABLE
L6565
L6565
Error Amplifier Block (see fig. 14b):
The Error Amplifier (E/A) inverting input is used in primary feedback technique to compare a partition of the voltage generated by the auxiliary winding with the internal reference, to achieve converter's output voltage regulation (see "Application Ideas", fig. 21). With secondary feedback (typically using a TL431 at the secondary side and an optocoupler to transfer output voltage information to the primary side through the isolation barrier) the E/A can be used as an inverting level-shifter to achieve negative feedback and shape the loop gain (see "Application Ideas", fig. 20). The E/A output is used typically for control loop compensation, realized with an RC network connected to the inverting input. With other secondary feedback techniques, the output is driven directly by an emitter-grounded optocoupler to modulate the duty cycle (the inverting input will be grounded in that case - see figure 20 in "Application Ideas").
Current Comparator, PWM Latch and Hiccup-mode OCP (see fig. 14b):
The current comparator senses the voltage across the current sense resistor (Rs) and, by comparing it with the programming signal delivered by the feedforward block, determines the exact time when the external MOSFET is to be switched off. The PWM latch avoids spurious switching of the MOSFET, which might result from the noise generated ("double-pulse suppression"). A comparator senses the voltage on the current sense input and disables the gate driver if the voltage at the pin exceeds 2 V. Such anomalous condition is typically generated by a short circuit on the secondary rectifier or on the secondary winding. To re-enable the driver, first the IC must be turned off and then can be restarted, that is the Vcc voltage must fall below the UVLO threshold. When the gate driver is disabled the quiescent current of the IC is unchanged and, since no energy is coming from the self-supply circuit, the Vcc capacitor will be discharged below the UVLO threshold after some time. Then the device will initiate a new start-up cycle. In case of failure of the secondary diode the resulting behavior will be a low-frequency intermittent operation (Hiccup-mode operation), with very low stress on the power circuit.
Gate Driver (see fig. 15):
A totem pole buffer, with 400mA source and sink capability, drives the external MOSFET. It is made up of a high-side NPN Darlington and a low-side MOSFET. In this way there is no need of an external diode clamp to prevent the voltage at the gate drive output (pin 7, GD) from being pulled too negative. An internal pull-down circuit holds the output low when the device is in UVLO conditions, to ensure that the external MOSFET cannot be turned on accidentally (e.g. at power-on).
Figure 15. Gate driver with UVLO pull-down
Vcc 8
L6565
7
DRIVER
GD
Q
UVLO
6 GND
11/17
L6565
TYPICAL APPLICATIONS
Figure 16. 50W Wide Range Mains SMPS for 14" TV
C6 4700pF/ 4KV C 7 4700pF/4KV
F1 2A fuse
Vin C23 88 to 100nF 264 Vac L1 15mH
NTC1 16R C25 C24 1nF 100nF
D1 1N4148 B1 2KBP04M C1 150 F 400 V R1 75k R2 75k C8 C2 8.2 nF 180 pF 250 V 630V
R9 4.7M 3 T1
R10 4.7M
C22 100pF 105 V 0.35 A
C26 1nF
R5 100 k
N1
8 1 D5 BYT01-400 C9 220 F 160V
D3
STTA106 4
N2
9
D6 BYW98-100 C10 470 F 25 V
14 V 1A
R8 22 C4 47F 25V 5 7 R3 3M VFF ZCD GD R20 22 k R6 100 D2 R7 10 1N4148 D4 1N4148
N3 Naux
10 5
IC1
L6565
3 2 1 COMP INV 6
Q1 STP7NB80FI
4 8
CS Vcc C27 220nF
R11 0.47 1 IC3 PC817 4 1 R15 1.8 k C12 100F 25V IC4 L7805 3 2
C3 1 nF
R4 16 K
GND
+5 V 50 mA C11 47 F 25V
R12 47 k R13 3.3 k DZ1 15 V R14 1.5 k
C5 2.2 nF
3
2 1 3
R16 220k C13 100nF
P1 100 k R18 150k
TRANSFORMER SPEC S: CORE: ETD29x16x10, N67 material or equivalent IC2 TL431 1 mm air gap for a primary inductance of 285 H N1: 48 T (24T+24T series connected), 2xAWG28 ( 0.37 mm) N2: 31 T, AWG28 N3: 5 T, AWG28 Naux: 5 T, AWG32 ( 0.24 mm)
2
R17 4.7 k
Figure 17. 40W Wide Range Mains SMPS for inkjet printer
2200pF 4KV
2A fuse
Vin 88 to 100nF 264 Vac 15mH
16R
1N4148
1nF 2KBP04M
BYW100-200 28V / 0.7A
75 k 56 k 2W 75 k STTA106
100nF
10 nF 250V N1
N2
BYW98-100 2 x 1000F 16V
2 x 470F 35V 12V / 1.5A
1nF
N3
GND
47 k 10
BYW100-50 5V / 0.5A 1N4148 N5 N4 470F 16V
47F
3 M
5
8
10
STP4NA80FP
220
7
L6565
3
10 nF 16 k
4 2 1 6 0.39 1/2 W
3.3 nF
PC817A
3.9k 270 k
100 nF
5.1k
PC817
TL431
TRANSFORMER SPECS: CORE: ETD29x16x10,3C85 material or equivalent 1 mm air gap for a primary inductance of 700 H N1: 75 T, AWG25 ( 0.51 mm) N2: 8 T, AWG25 N3: 7 T, AWG20 ( 0.89 mm) N4: 3 T, AWG25 N5: 7 T, AWG32 ( 0.24 mm)
2.7 k
12/17
L6565
APPLICATION IDEAS
Here follows a series of ideas/suggestions aimed at either improving performance or solving common application issues of L6565-based power supplies.
Figure 18. Enhanced turn-off for big MOSFET's drive
Vcc 8
7
DRIVER
GD Q
BC327
L6565
6 GND
Rs
Figure 19. Latched shutdown on: a) feedback disconnection; b) overload or short circuit
Vcc 8 Vcc 8
L6565
L6565
2 COMP
a)
Figure 20. Secondary Feedback loop configurations
b)
Vout
Vout
Vout
L6565
8 Vcc INV 1 COMP 2
L6565
2 COMP RA 1 INV RB 8 Vcc
ICOMP TL431 TL431
L6565
1 INV 4 CS Roff Rs
TL431
a)
b)
c)
13/17
L6565
Figure 21. Primary Feedback loop configurations
Vcc COMP RH 2 8 RH COMP 2 Vcc 8
1 INV + RL 2.5V GND 6
1
E/A
to VFF block RL
INV + 2.5V
E/A
to VFF block
L6565
GND
6
L6565
a)
b)
Figure 22. Protection against secondary feedback disconnection by primary regulation take-over
Vcc 15 V 8 INV 1
Figure 24. Remote ON/OFF control
L6565
5 ZCD OFF ON
L6565
2 COMP
BC337
2.2 k
Figure 25. Low-consumption start-up circuit Figure 23. Leading edge blanking circuit for enhanced primary regulation
Vac
+Vin
BC327
1N4148 Vcc
R CSTART 1N4148 Vcc
470 pF 2.7 k
L6565
1N4148
8
CSUPPLY
L6565
6
GND
GND
RELATED DOCUMENTATION [1] "L6565, QUASI-RESONANT CONTROLLER" (AN1326) [2] "25W QUASI-RESONANT FLYBACK CONVERTER FOR SET-TOP BOX APPLICATIONS USING THE L6565" (AN1376) [3] "EVAL6565N, 30W AC-DC ADAPTER WITH THE L6565 QUASI-RESONANT PWM CONTROLLER" (AN1439).
14/17
L6565
mm DIM. MIN. A a1 B b b1 D E e e3 e4 F I L Z 3.18 7.95 2.54 7.62 7.62 6.6 5.08 3.81 1.52 0.125 0.51 1.15 0.356 0.204 1.65 0.55 0.304 10.92 9.75 0.313 TYP. 3.32 0.020 0.045 0.014 0.008 MAX. MIN.
inch TYP. 0.131 MAX.
OUTLINE AND MECHANICAL DATA
0.065 0.022 0.012 0.430 0.384 0.100 0.300 0.300 0.260 0.200 0.150 0.060
Minidip
15/17
L6565
DIM. MIN. A a1 a2 a3 b b1 C c1 D (1) E e e3 F (1) L M S 3.8 0.4 4.8 5.8 0.65 0.35 0.19 0.25 0.1
mm TYP. MAX. 1.75 0.25 1.65 0.85 0.48 0.25 0.5 0.026 0.014 0.007 0.010 0.004 MIN.
inch TYP. MAX. 0.069 0.010 0.065 0.033 0.019 0.010 0.020
OUTLINE AND MECHANICAL DATA
45 (typ.) 5.0 6.2 1.27 3.81 4.0 1.27 0.6 8 (max.) 0.15 0.016 0.189 0.228 0.050 0.150 0.157 0.050 0.024 0.197 0.244
SO8
(1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch).
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L6565
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